The inventive concepts relate to a wafer level package, and more particularly, to a wafer level package that includes dissimilar molding members having different coefficients of thermal expansion (CTEs) with respect to a plurality of semiconductor chips mounted on a substrate.
Even though volumes of electronic devices decrease, a large capacity of data is processed by the electronic devices. Accordingly, the degree of integration of semiconductor devices used in such electronic devices increases. Particularly, recently, a semiconductor package process for reducing the size of a wafer level package to that of a semiconductor chip while maintaining characteristics of a bare chip is being researched and developed. However, since warpage occurs in the wafer level package due to a difference between coefficients of thermal expansion (CTEs) of a substrate and a molding member, it may be difficult to meet expectations with regard to chucking for a processing facility. Such a problem is serious in the processing of large-diameter waters, which is a current trend in producing wafer level packages.